Only three companies in the world can perform mass production of the most advanced computer chips with incredible accuracy. Last month, a Japanese startup took the first step to become the fourth. On April 1st, a key milestone was achieved. Based on IBM’s nanosheet transistor structure, it started and tested the test line of its 2-nanometer node chip using the formula developed in cooperation with IBM. Tell IEEE Spectrum that its new wafer factory in Chitose has installed more than 200 cutting-edge equipment, including Keystone components, a state-of-the-art extreme ultraviolet (EUV) lithography system worth more than 300 million dollars, and is now ready to put into operation.

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"We broke ground in September 2023," said Henri Richard, president of Design Solutions, which was founded in Santa Clara, Silicon Valley last April to supervise the business development in the United States. "Therefore, at the beginning of the second quarter of 2025, we have made the first exposure to the EUV lithography system, and now we are ready to start trial production, which is really amazing."

As for when Rapidus will ship the first batch of test chips, Atsuyoshi Koike, CEO of Rapidus, told the Japan Times in April, "The prototype chip may be produced in July. Although in a company statement, it clarified the media reports on negotiations with customers, the company said that it was "discussing with many potential customers, from large mature enterprises to AI startups".

5 trillion yen: capital Rapidus predicts the need for mass production.

Founded in August 2020, Rapidus is supported by a consortium of eight domestic companies: Denso, Armored Man, MUFJ Bank, NEC, NTT, Softbank, Sony and Toyota. But it turns out that the support of the central government is more important, which is part of the efforts to revitalize the country’s advanced semiconductor industry. Japan’s support stems from national security concerns, because the country relies on overseas suppliers who may be vulnerable to provide cutting-edge chips. For the same reason, the United States has also taken action to reduce its dependence. So far, the total amount of government subsidies is 1.72 trillion yen ($12 billion). However, the equity investment of the eight founders is still only 7.3 billion yen (US$ 51 million), which raises concerns about the future of Rapidus. The new foundry estimates that it needs about 5 trillion yen ($35 billion) to achieve its mass production goal.

However, the situation of Rapidus is no different from that of Taiwan Integrated Circuit Manufacturing Co., Ltd. (TSMC), which was established in the 1990s. Atsushi Osanai, a professor at Waseda University’s Graduate School of Business and Finance, pointed out that at that time, like Japan, the Taiwan Province government supported the startup, while the private company was "not enthusiastic at first". "Similarly, Japanese private companies have a wait-and-see attitude towards Rapidus. The key factor will be whether the government provides sufficient support for Rapidus [to stimulate] the private sector.

Rapidus and TSMC

Despite the rapid start of Rapidus, its delivery date of 2 nm in 2027 may be two years behind TSMC, Intel and Samsung, the three leading silicon producers in the industry. It is reported that these three companies may start mass production of 2 nm chips in the second half of this year.

In order to catch up and compete, Rapidus is adopting a different method from the large-scale silicon wafer production mode favored by the three major manufacturers. The business model, represented by TSMC, focuses on processing large quantities of wafers with GPU and CPU, with high yield, and relies on rigid processing methods that are only gradually improved. In contrast, Rapidus will use a single wafer process to produce application-specific chips, produce customized chips for niche markets, and only produce large quantities of orders in the future.

As the name implies, the single wafer method processes each wafer individually, rather than in batches. Although many wafers can pass through the production line at the same time, each wafer is handled separately at each stage of the process. Rapidus will also apply a newly developed scheme called Design and Manufacturing Collaborative Optimization (DMCO). The company claims that this will promote design by linking design with manufacturing, which will also help offset the reduced throughput due to the elimination of batch processing. By using AI to optimize production parameters, DMCO aims to improve design speed and yield. This requires sensors to be widely used in the equipment to measure parameters such as temperature, gas density and reaction rate, so as to obtain a large number of production data for AI analysis.

"This will enable us to measure the processing process of a single wafer, learn from the results and feed the data back to the system quickly," Richard explained. "In order to increase the output, the parameters must be constantly adjusted, and these changes depend on the data learned during the processing."

In addition, he added, the wafer factory is using "a revolutionary grid transportation system, which enables us to move the wafer to any position during the processing, thus avoiding the traffic jam when the machine stops or problems occur in the standard wafer factory with linear transportation system."

Tadahiro Kuroda, an engineering professor at the University of Tokyo, said: "The idea of obtaining a large amount of data from the manufacturing process and feeding it back [to the system] to increase production more quickly will shorten the time to market." Tadahiro Kuroda, an engineering professor at the University of Tokyo, said that he worked in Toshiba’s semiconductor department for 18 years and then entered academia. "This is an ideal scene for semiconductor manufacturing, which is very meaningful."

However, because a large number of new technologies depend on a large number of new technologies, Rapidus may encounter initial problems, which may extend the time required to deliver products to customers in batches. At the same time, competitors did not wait for it to catch up. In April, TSMC launched its next-generation A14 process (equivalent to 1.4 nm node chip), and plans to "put into production in 2028".

"Technically, the success of Rapidus depends on whether the semiconductor prototype developed for mass production in 2027 goes smoothly," Osanai said. "Achieving mass production in two years represents a key condition for the company’s success."

Other experts are more optimistic. In view of the expected huge growth of AI applications and emerging AI data centers, and the consequent leap in power consumption, "there will be a great demand for 2-nanometer chips," Kuroda said, because these semiconductors are expected to reduce power consumption by more than 30% compared with today’s leading silicon. "Therefore, the demand for artificial intelligence-related semiconductors is expected to exceed the production capacity of current foundries."

If the latter viewpoint is successful, and Rapidus can achieve its mass production goal on time, then the government-supported effort to regain Japan’s status as an advanced power may become a successful bet, not a rash gamble.